In conventional transistor-transistor logic (TTL) and diode-transistor logic (DTL), logical values corresponding to binary "1" and "0" are ordinarily represented by a high level voltage V.sub.oH, for example greater than 2.5 volts and a low level voltage V.sub.oL, for example less than 0.8 volts. In positive logic, the high level binary "1" is derived from a voltage source V.sub.cc which sources current to the output when a binary "1" is to be delivered by the logic gate. When a binary "0" is required at the output, the logic gate "sinks" the current from the output load to a low level so that the low level voltage V.sub.oL, appears at the output of the logic gate. Thus, the typical TTL logic gate functions by "sourcing" and "sinking" current at the output according to whether a binary "1" (high level voltage) or a binary "0" (low level voltage) is the desired outcome of previously executed logical operations. In negative logic the representation of binary 1 and 0 by high and low level voltage is reversed.
A conventional TTL tristate output device is illustrated in FIG. 1. Several elements or stages can be identified in such a TTL output gate. The "pullup" 11 for sourcing current from the higher level voltage V.sub.cc corresponding to binary 1 consists of transistors Q3 and Q4 forming a Darlington transistor that can supply current between the high level voltage source V.sub.cc and the output V.sub.out. The "pulldown" element or stage 12 for sinking current and voltage from the output to ground consists of transistor Q2 with conventional squaring network transistor Q5 at its base. The phase splitter element or stage 13 consists of transistor Q1 which receives the data signal input to the gate in the form of a high or low level voltage at V.sub.in and controls the pullup and pulldown elements for either sourcing or sinking current at the output 14 as determined by the data signal input to the gate.
When a low level voltage input appears at the input 15, a low voltage also appears at the base of phase splitter transistor Q1 and this transistor no longer conducts current through its collector to emitter thereby turning off transistor Q2. The output V.sub.out of the gate is therefore isolated from ground. Because Q1 is non-conducting, the high level voltage V.sub.cc appears at the base of sourcing transistor Q3 permitting the transistor Q3 to conduct to the base of Q4 which in turn becomes conducting and "sources" current from V.sub.cc to the output V.sub.out. The TTL logic gate is therefore inherently inverting as a binary 0 at the input V.sub.in represented by voltage level V.sub.oL generates a binary 1 at the output represented by voltage level V.sub.oH.
When a binary 1 appears at the input current from R8 supplies base drive to transistor Q1, Q1 becomes conducting, sinking current from the base of Q3 and therefore turning off the Darlington transistor current source represented by transistors Q3 and Q4. Current from high level voltage V.sub.cc is therefore no longer sourced to the output 14. At the same time, pulldown transistor Q2 becomes conducting through its collector to emitter to ground as a result of the current supplied to its base and begins to discharge whatever load may be coupled to the output 14 of the gate. One factor determining how transistor Q2 discharges the load, drawing the output V.sub.out to the low level voltage V.sub.o, is the base current delivered to Q2. During transition from high to low level voltage at the output 14, the pulldown element 12 must sink current not only from whatever load capacitance may be coupled at the output but also from resistive loads of the other logic devices it is connected to. Since the emitter current of phase splitter transistor Q1 determines the base current of pulldown element transistor Q2, the collector resistor R.sub.c, of the phase splitter Q1 is selected to the relatively small to permit a large current to drive pulldown transistor Q2 to greater conduction.
As shown in FIG. 1, some of the transistor and diode components are typically Schottky diodes and transistors indicated by the opposite square hooks in the schematic symbols. The Schottky clamping effected by an internal modification in these devices produces quicker turn-off during switching. A transistor logic output gate of the type illustrated in FIG. 1 while affording acceptable speed in switching and current sinking capability by selection of a low collector resistance R.sub.c, suffers the disadvantage of high power consumption in the high impedance third state as will become apparent.
The element added to the output gate of FIG. 1 to create the high impedance third state at V.sub.out and generally provide a tristate output device instead of a bistate output device is the enable gate 18 represented in part by transistor Q6 which, when conducting, provides a route to ground from the base of pullup transistor 11 for high level voltage source V.sub.cc through one way diode D3. The base of phase splitter transistor Q1 and therefore any data input signal also finds a path to ground through the collector to emitter of enable gate transistor Q6 and one way diode D4. Ordinarily transistor Q6 is non-conducting so that the aforesaid routes to ground are blocked. In this condition, the output gate functions as a bistate output device in the manner already described, sinking or sourcing current at the output 14 according to whether the pulldown or pullup element is conducting.
In order to establish a high impedance third state at V.sub.out, the enable gate 18 is activated by a signal at the base of transistor Q6 so that it becomes conducting through its collector to emitter to ground. In this state, the enable gate effectively sinks all current to the elements of the output gate including the pullup, and phase splitter stages (and therefore indirectly the pulldown element) by providing a direct route to ground through R.sub.c for the high level voltage V.sub.cc. With all of the elements deprived of base current, the output effectively becomes a high impedance to any exterior circuitry. In this condition, the tristate output device will neither source nor sink current at the output 14 and will behave effectively as if nothing were there. Such a tristate device is therefore particularly applicable and suitable for applications in which a plurality of output gates are tied together or coupled to a common bus structure. In such common bus applications only one output, that is only one of the gates coupled to the bus structure determines the voltage (high or low) of the bus while the other outputs for the remaining gates are in the high impedance third state.
As further illustrated, the conventional enable gate 18 incorporated into the TTL output device of FIG. 1 is itself a bistate TTL gate where transistor Q6 forms the pulldown element 20 coupled with squaring circuit 21 at its base. The other elements include the Darlington transistor pullup element 22, phase splitter 23 and enable control signal input 24.
The power consumption characteristics of the output gate as illustrated in FIG. 1 are, however, sacrificed by adding the enable gate to achieve the tristate TTL output illustrated in FIG. 1. To explain this compromise more fully, reference is made to collector resistance R.sub.c of phase splitter transistor Q1 whose resistance must be low enough to assure that the Q1 emitter current to the base of Q2 is large enough to allow Q2 to sink the required load current. The problem arises in attempting to combine both the enable gate 18 which makes possible the high impedance third state and the low resistance R.sub.c which determines the current through the phase splitter 13 to the base of the pulldown transistor Q2. When the enable gate is activated and transistor Q6 conducting to ground, resistance R.sub.c affords a relatively low impedance route directly from the high level voltage source V.sub.cc through the enable gate to ground. The high impedance third state is therefore the condition for maximum power dissipation in phase splitter collector resistor R.sub.c. In this condition the device is in the high impedance state performing no logical operation and consuming maximum power.
The foregoing account represents the closest prior art and state of the art pertinent to the present invention known to the inventor. In terms of published documentation, a recent representative presentation exemplifying this prior art and state of the art in DTL and TTL bistate and tristate output technology is found in MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, LOW POWER SCHOTTKY, TTL, DATA SELECTORS/MULTIPLEXERS, MONOLITHIC SILICON MIL-M-38510/309A (USAF), Jan. 4, 1978, superceding MIL-M-38510/309 (USAF), Feb. 28, 1977, Rome Air Development Center, Department of the Air Force, (RADC) (RBRD), Griffiss AFB, N.Y. 13341. Particularly pertinent to tristate output devices in this milspec are examples of commercial type microcircuits under designation numbers 54LS251 through 54LS258 corresponding to device types 05 through 08 and generally 54LS microcircuits illustrated at pages 44 through 71. Additional documentation of the prior art and state of the art known to the inventor and here presented can be found in current catalogs and data books of the commercial semiconductor microcircuit and integrated circuit manufacturers such as the LOW POWER SCHOTTKY DATA BOOK of the Fairchild Camera and Instrument Corporation, 464 Ellis Street, Mountain View, Calif. 94942, Copyright 1977. Pertinent portions for tristate output devices include the chapter "Circuit Characteristics" pp. 2-3 through 2-7 and applications to buffers, bus drivers and tristate outputs in the 54LS and 74LS series of 200 and greater beginning at page 5-187.